A Netlist Reduction Algorithm to Symbolic Circuit Analysis
P. Barrera (STMicroelectronics, Catania, Italy), J. Broz (ITWM, Kaiserslautern, Germany), T. Halfmann (ITWM, Kaiserslautern, Germany)
A new reduction algorithm in the area of symbolic circuit analysis is presented. The reduction of a netlist as well as of the model order complexity are important modelling issues which help to speed up the process of integrated circuit design[1]. The proposed method eliminates nodes from a netlist topology assuring a user-given accuracy margin. The algorihm is based on the decision diagram derived from the circuit topology and considers low memory storage issues in order to efficiently carry out the simplification. Starting from the application of a spiral inductor test case [2] efficiency is evaluated. The reduced system complexity in terms of netlist nodes and model order encourage the application to other industrial test cases.
[1] T. Halfmann, T. Wichmann, "Symbolic Methods in Industrial Analog
Circuit Design", Scientific Computing in Electrical Engineering (SCEE 2004), Capo D'Orlando, Italy, Sep. 2004
[2] A. Ciccazzo, G. Greco and S. Rinaudo Coupled EM and Circuit
Simulation Flow for Integrated Spiral Inductor Proceedings of SCEE2004 - Scientific
Computing in Electrical Engineering 5-9 September 2004 Capo d'Orlando, Italy